DCE Software Design Document (DCE SDD)

History of the Development of the DCE SDD

Summary written on 12/9/1999
Last Updated on 12/4/2000

The following is a summary of the long, and tortured history of the DCE SDD Development Plan:

  1. BATC and CU travel to UCB for the 'November' meeting (DCE SDD Development I) the week 11/15/1999. (Rob/Allison/Ken/Daniel/Geoff) - Done
  2. Material from the 'November' meeting incorporated into DCE SDD Top-Level Design by 12/6/1999. (Rob) - Done
  3. Draft of the Top-Level Design to be released on 12/6/1999 for review by UCB. (Rob/Ken) - Done
  4. UCB to deliver redlines of Top-Level Design by 12/13/1999. (Daniel) - Done
  5. Material from the 'November' meeting incorporated into DCE SDD Detailed Design by 12/17/1999. (Rob/Allison/Ken) - Done
  6. Draft of the Detailed Design to be released on 12/17/1999 for review by UCB. (Rob/Allison/Ken) - Done
  7. UCB to deliver redlines of Detailed Design by 1/04/2000. (Daniel/Geoff)- Done
  8. UCB responses to actions items from the 'November' meeting delivered by 1/04/2000. (Daniel/Geoff/Barry)- Done
  9. UCB travels to Boulder for the 'January' meeting (DCE SDD Development II) from 1/04 - 1/06/2000. (Daniel/Geoff/Rob/Allison/Ken)- Done
  10. UCB/BATC/CU responses to actions items from the 'January' meeting delivered by 1/13/2000. (Daniel/Geoff/Rob/Allison/Ken)- Done
  11. All redlines and material from the 'January' meeting incorporated into DCE SDD by 1/18/2000. (Rob/Allison/Ken)- Done
  12. DCE SDD released for internal review by BATC/UCB/CU on 1/18/2000. (Rob/Ken)- Done
  13. All redlines from the internal review of the DCE SDD due by 1/24/2000. (BATC/UCB/CU)- Done
  14. All redlines from internal review incorporated into DCE SDD by 1/31/2000. (Rob/Allison/Ken)- Done
  15. DCE SDD released for formal review by the entire HST Software Team on 1/31/2000. (Rob/Ken)- Done
  16. DCE SDD scrubbed for Action Items from the 'October' meeting (DCE Software Design Review) by 2/4/2000. (Ken)- Done
  17. DCE FSW "Delta" Design Review at CASA-ARL, set for 2/18/2000 at 9:00AM. (Ken)- Done

  18. August - October, 2000: Significant Change to DCE FSW Development Approach - See DCE SDD Information for details.- In Progress

DCE Software Design Document

DCE Software Design Document (PDF) - Information Outdated

DCE FSW Flow Diagrams - Information Outdated

Action Items from the 'February 2000' DCE "Delta" Software Design Review

Action Items from the 'January 2000' Meeting (DCE SDD Development II)

  1. Daniel: Provide Memory Map of the 8051 Internal Registers.
  2. Daniel: Provide a drawing of the DCE software development flow. Show how your Design of using a single source code set flows down to a single 'object' file from the compiler, and then how the link phase produces three separate executable images (Boot, LCA, UCA) - based on the absolute memory addressing of these areas.
  3. Daniel: Provide a list of the software development tool documentation references not already listed in Section 2. (i.e., Archimedes)
  4. Daniel: Provide an ABS file with Symbol information included.
  5. Daniel: Verify that all calculated CRC values are non-zero (for a reasonable input parameter space).
  6. Geoff: Provide a definitive answer to what UCB wants to do about the parameter 'TOGGLE' in the DCE Jump command.
  7. Geoff: Remove the commands LFDPEEK and LFDPROM from the FUV Detector ICD Appendices.
  8. Geoff: Create two new DCE HSK mnemonics for the 'Target' HV Voltage. (Note: The names LFHVTGTA and LFHVTGTB were informally agreed upon by the meetings participants.)
  9. Ken: Add appropriate contract information to the TBD listed in Section 1.1.
  10. Rob: Fold-in the pertinent information from the agreement on HV State Bit behavior (see links below) into the DCE SDD, in an appropriate section - possibly Section 4.2.7.
  11. Rob: Create a drawing to show how the three different executable code images (BOOT, LCA, UCA - as above) occupy different memory areas.
  12. Allison: Create a new CS Macro to 'clear' (i.e., zero-fill) the DCE HVI and AUXI Buffer & Histogram areas.

Behavior of DCE FSW HV State Bits (LFHSTATE)

Technical Evaluation Report (COS-11-0013) discusses the behavior of the DCE FSW HV State Bits (LFHSTATE) in response to recognized "events" which drive HV State Transitions.

Action Items from the 'November 1999' Meeting (DCE SDD Development I)

  1. Daniel: Be prepared to review and give a detailed summary of the how Timing works in the DCE Code. e.g., How is 49 ticks per second computed? What is the 170 ticks per second timer based on?
  2. Daniel: Provide the correct order for Task Execution within the Executive Loop.
  3. Geoff: Verify actuator turn-on sequence at a hardware level.
  4. Geoff: Provide Figure 3.1-3 and Hardware Information to Rob when the updated ICD is released.
  5. Daniel, Geoff and UCB: Decide how your plan to report SW and HW Status bits back in HSK. (e.g., HV and Door Status Bits.) Decide which DCE SW items will be new HSK mnemonics, and which will simply be internal variables in the DCE FSW. If you choose to have separate mnemonics for HW and SW Status bits - distribute that information to the FSW Team. Also, update the DCE HSK Database, and Appendix D in the ICD to reflect this decision.
  6. Daniel and Geoff: Figure out what the current DCE FSW Reset Vector does regarding the door and Aux power. Does a reset (either POR and WatchDog) stop the door and shut off Aux power? If the current design is what you propose to keep for COS, make sure we have summarized the DCE reset information properly in the DCE SDD.
  7. Daniel: Summarize the proposal you described for the process of "saving HSK information" in the event of a reset. i.e., document your idea for the scheme of copying the entire Housekeeping Buffer to the transfer area upon a reset.
  8. Barry, Daniel and Geoff: Document the possible Budget and Schedule impact for the proposed modification to your Boot and Operate code images and modes. i.e., The rest of us feel that the current Boot design will NOT be approved as is, without a clear understanding of how modifying the current design will negatively impact schedule and budget.

Action Items from the 'October 1999' DCE Software Design Review

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