|Number||Document||Topic||Comment||Response||Response Due Date||Closure Approval||Closed Date||Disposition|
|1||DCE SDD||System Overview||Please add a system overview section - describing how the DCE fits into the COS science instrument. Include a top level block diagram.||Updated DCE SDD contains overview section with top level block diagram. System Overview in Section 1.2, Block Diagram in Figure 1.2-1, Functional Overview of FUV Detector in Section 3.1.||11/12/1999||3||01/27/2000||CLOSED|
|2||DCE SDD: Section: 1.3||Change Title Name||Change the title of section 1.3 from COS to DCE||N/A in the revised DCE SDD.||11/12/1999||3||01/27/2000||CLOSED|
|3||DCE SDD||Architecture Overview||Include an architecture overview:
1. Define CSCI Level I/O
2. Define CSCs
3. Define CSC I/O
4. Provide a functional/process flow description for each CSC.
5. Include real-time features such as exception handling.
|Updated DCE SDD contains architecture overview: Section 3.2 (CSCs), Section 3.3 (Control Flow), Section 3.4 (Data Flow). Section 4.2 gives the Software Architecture overview - with discussions of the Operating System, Resets and Initialization, and ISR & Task descriptions.||11/12/1999||118||03/01/2000||CLOSED|
|4||DCE SDD: Section: 4.4.3||State Diagrams||Modify State Diagrams to be more clear:
1. Arrows should have event names showing how to transitions from one state to another.
2. State Names should not include the event. e.g. POR Boot & Watchdog Boot should just be Boot - with POR & Watchdog as events.
|State information in previous DCE SDD has been broken down into discussions of Modes (Boot/Operate) and description of how the DCE performs various Tasks. System states, per say, are no longer discussed in the DCE SDD. Instead, DCE State information has been (mostly) relegated to operational documents, such as DM-05 and OP-01.||11/12/1999||118||03/01/2000||CLOSED|
|5||DCE SDD: Section: 4.4.3||State Diagrams||Need better description of the states and transitions.||State information in previous DCE SDD has been broken down into discussions of Modes (Boot/Operate) and description of how the DCE performs various Tasks. System states, per say, are no longer discussed in the DCE SDD. Instead, DCE State information has been (mostly) relegated to operational documents, such as DM-05 and OP-01.||11/12/1999||118||03/01/2000||CLOSED|
|6||DCE SDD: Section: 5.2||Function Lists||Need to include a detailed function list for each CSC with detailed logic flow.||Detailed Design Section contains logic flows for all DCE Tasks and Commands. Tasks are described in Section 4.2.3 of the Revised DCE SDD. Commands are described in Section 4.28 of the Revised DCE SDD.||11/12/1999||118||03/01/2000||CLOSED|
|7||DCE SDD: Section: 5.2||Software Reuse||Include information on SW reuse if possible. This will dictate the amount of testing required.||Detailed Design Section contains Reuse information.||11/12/1999||3||01/27/2000||CLOSED|
|8||DCE SDD: Section: 7||Traceability Matrix||Complete the requirement traceability matrix.
(Added 11/1/99 - To incorporate AI comments from Sue Ross): The Traceability Matrix in the DCE SDD should show which requirements are satisfied by which tasks. The DCE Software Test Plan should show which test(s) satisfy which requirements.
|Section 6 of revised DCE SDD contains tracibility matrix for FSW requirements. Includes CSC information.||11/12/1999||3||01/27/2000||CLOSED|
|9||DCE SDD||Galex References||Remove all references to Galex.||References to Galex remain in sections 4.1.1 and 5. References in these sections are appropriate - as they discuss code reuse and the development environment.||11/12/1999||3||01/27/2000||CLOSED|
|10||DCE SDD: Section: 1.1||Identification||In second paragraph, list the contract between UCB and CU. Specify that document is written in accordance with the SMC-1050 HST Data Requirements Document, part DM-03.||Done||11/12/1999||3||01/27/2000||CLOSED|
|11||DCE SDD||DCE Counts vs. Count Rates||Scrub document and make certain that - where appropriate - the document specifies Count Rates, not Counts. (e.g., Section 1.3, 4.4, 22.214.171.124)||Done||11/12/1999||3||01/27/2000||CLOSED|
|12||DCE SDD: Section: 1.3||Verbiage Change||Drop use of "will", when describing the design of the DCE FSW. e.g., Don't say, "The DCE FSW will implement a command interface...", say "The DCE FSW implements a command interface...".||N/A in rewritten DCE SDD.||11/12/1999||3||01/27/2000||CLOSED|
|13||DCE SDD: Section: 1.4||Add text to sentence||In the third sentence of Section 1.4, add the text "COS FSW" in front of Software User's Guide.||N/A in rewritten DCE SDD.||11/12/1999||3||01/27/2000||CLOSED|
|14||DCE SDD: Section: 2.1||CS FSW RD||Add document number IN0090-619 to the CS FSW Requirements Document.
Add reference to the COS Control Section Software Design Document, IN0090-623.
|Document referenced as DM-03, as per other HST SDD references.||11/12/1999||3||02/01/2000||CLOSED|
|15||DCE SDD: Section: 3||Acronyms/Abbreviations||Add Acronyms/Abbreviations for the following:
ADC, BBIT, CRP, CS, DAC, ISR, PHA, POR, RTOS, LCA, UCA, SIO, OS, I/F, MUX, PH, MCP, PCA, CLP, ECO, MON51.
In addition, when an acronym is used for the first time in the document, spell it out completely. If an acronym is used only once in the document - you don't need to add it to the acronym list.
|N/A. Updated DCE SDD will need to be independently scrubbed for Acronyms.||11/12/1999||3||02/01/2000||CLOSED|
|16||DCE SDD: Section: 4.1||Add DCE to FSW||Where appropriate, use the qualifier "DCE" when referring to Flight Software (or FSW). e.g., Section 4.1, Paragraph 1, Sentence 1.||Done||11/12/1999||3||02/01/2000||CLOSED|
|17||DCE SDD||I/O||Use capital letters when referring to I/O (Input/Output). (Scrub entire document for i/o.)||Done||11/12/1999||3||02/01/2000||CLOSED|
|18||DCE SDD||Figure Numbers||Match Figure Numbers with the appropriate document section. e.g., Figure 1 should be Figure 4.1-1.
Also, refer to Figure Numbers explicitly in the text, don't say figure 'above'. e.g. First sentence in Section 4.4.2.
|19||DCE SDD: Section: 126.96.36.199||Formatting (Font/Style)||Use same Font(s) and Formatting throughout the Document. e.g., Section 188.8.131.52 uses a different font than the rest of Section 4.||Done||11/12/1999||3||01/27/2000||CLOSED|
|20||DCE SDD||Current Limit (ilimit)||Either add 'ilimit' to the Acronym list, or write out the words 'current limit'. e.g., Section 184.108.40.206, 220.127.116.11||Done||11/12/1999||3||01/27/2000||CLOSED|
|21||DCE SDD: Section: 4.1.2||Harvard and Von Neumann Architectures||Define/Describe Harvard and Von Neumann Architectures before these terms are used to describe the DCE architecture. e.g., The explanation in Section 4.2.1 should come before the use of Von Neumann in Section 4.1.2.||Addressed in 18.104.22.168.1 of the new DCE SDD.||11/12/1999||3||02/29/2000||CLOSED|
|22||DCE SDD: Section: 4.3.2||CMD format||Output files of type .CMD are defined as an uploadable script in FUSE eGSE format. What about the COS eGSE format? Are they the same? Explain.||Section 5.2.1 of updated DCE SDD describes .CSF files - which are code images in UCB EGSE format.||11/12/1999||3||02/01/2000||CLOSED|
|23||DCE SDD: Section: 4.4||CDC/TDC||I don't believe there are CDC's in the COS FUV Detector. (We are flying an XDL, not a DDL - so I believe we have TDC's on both dispersion and cross-dispersion axes.) If this is correct, remove all references to CDC's.||Revised DCE SDD does not mention CDCs.||11/12/1999||3||01/27/2000||CLOSED|
|24||DCE SDD: Section: 4.4||Figure of Simplified Data Flow||What is 'I/F' in the Simplified Data Flow Diagram (Figure 4)? Are CDC's really part of the science data channel in COS? (See Action #23).||N/A in rewritten DCE SDD.||11/12/1999||3||01/27/2000||CLOSED|
|25||DCE SDD: Section: 22.214.171.124||Command Rx||Describe further the reserved bits used for 'Special Commands'.||N/A. DCE Commands are now described in detail in Section 4.2.8 of revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|26||DCE SDD: Section: 126.96.36.199||Power-On Reset||Move sentence describing Watchdog Reset from Section 188.8.131.52 down to Section 184.108.40.206 - which is the description of the Watchdog Reset||N/A in rewritten DCE SDD.||11/12/1999||3||01/27/2000||CLOSED|
|27||DCE SDD: Section: 220.127.116.11||HVI and AUXI Histogram and Buffer Areas||Describe HVI and AUXI Histogram and Buffer Areas, and how information is stored in them during HV operations.||Briefly described in Sections 18.104.22.168 and 22.214.171.124 of updated DCE SDD. Most of this information will be contained in the DCE Hardware/Software Interface Document (An In Development BATC SER.)||11/12/1999||3||02/01/2000||CLOSED|
|28||DCE SDD||Consistent FUV Detector Nomenclature||The Descriptive syntax in the DCE Software Design Document is not consistent with syntax used in other UCB Documents. e.g., there are no COS Detector Interface Electronics (DIE) - COS uses Detector Control Electronics (DCE). Since this document will be used for years to come - and will possibly be used to locate drawings, diagrams, schematics and other documents - it is imperative that the correct nomenclature be used. UCB Systems Engineering needs to scrub the document and verify accuracy and correctness of all physical descriptions, drawings, figures, etc...||Redlines to the document which would have made the document consistent with COS nomenclature were submitted shortly after the document was first made available. The same uncorrected document was released for review before these redlines were incorporated. Daniel has the action to incorporate those redlines into the next revision.||11/12/1999||3||02/29/2000||CLOSED|
|29||DCE SDD - Cover Page||Document Number for DCE SDD||The Software Design Document for the DCE has been assigned the following number: COS-UCB-009. Update the cover page appropriately.||Done||11/12/1999||3||01/27/2000||CLOSED|
|30||DCE SDD: Section: 5.1.4||FMECA - DCE RAM||Examine the FUV Detector Subsystem FMECA/CIL report (UCB-COS-DOC-1027) and determine if the DCE RAM is at risk. If it is not, then do not add the requirement for the DCE to be able to perform remapping of the memory below 8000 (HEX).||There are additional reasons to pursue the remapping of memory below 8000H. (Called Special Bank Memory Switching.) Without this functionality, ISR code cannot be changed for Operate Mode - as the ISRs live in the memory area of PROM - unless this memory area can be remapped to RAM. This issue will be readdressed in an AI for the updated DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|31||DCE SDD||Change Actel to FPGA in Document||Change all uses of 'Actel' to 'FPGA' in the document. Add FPGA to acronym list.||Updated DCE SDD does not call out FPGAs or Actels (except in Section 126.96.36.199.3 - new Action Item will be issued for this section.) Specific H/W information will be described in DCE HW/SW Interface Document (An In Development BATC SER.)||11/12/1999||3||02/01/2000||CLOSED|
|32||DCE SDD||PHA, PHD, PH||Use of the term 'PHA' will be dropped from the document. PHD and PH will be used appropriately instead.||Done||11/12/1999||3||02/01/2000||CLOSED|
|33||DCE SDD: Section: 2.1||Modify List of Related Documentation||Remove the reference to 'Appendix to Software User's Guide, BATC'.
Add reference to 'FUV Software User's Guide', COS-UCB-TBD.
|Reference added for COS Flight Software Users Manual, DM-03.||11/12/1999||3||02/01/2000||CLOSED|
|34||DCE SDD||FSW Operation Description||In the early part of Section 4, give an overview of how the software works. e.g., The information in section 5.2.2 is essential to understanding the DCE FSW, especially because there is no RTOS. A general description of how the software executes, and how tasks are processed in round-robin fashion, would make understanding the rest of the document much easier.||This information is now documented in Sections 3.3, 3.4 and 4.2||11/12/1999||3||02/01/2000||CLOSED|
|35||DCE SDD||DCE Commands and Execution Times||No where in the SDD do you list the DCE commands or what they do. These commands MUST be part of the SDD. Also, add information about the execution time of commands - and the impact on the various background tasks.||Fully documented in Section 4.2.8 of the revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|36||DCE SDD: Section: 5.2||Task Event Descriptions||In the Event Descriptions for the Tasks in Section 5.2, include the list of commands that relate to that task.
Also, include which tasks (and which commands) are available in Boot/Operate modes.
|Section 4.2.8 of the new DCE SDD gives the full list of commands in four major areas: DCE Internal Commands, Digitizer Commands, HV Commands, and Door Commands. (Boot/Operate mode information is given.) While a cross-reference is NOT given for commands and tasks, the descriptions for both should be enough to satisfy the intent of this AI.||11/12/1999||122||02/29/2000||CLOSED|
|37||DCE SDD: Section: 188.8.131.52||Boot/Operate Mode Information||Early in the Preliminary Design Section there should be information about the Boot and Operate modes of the DCE FSW. This information should go up front where the overview of FSW execution is described. (See AI #34).||New DCE SDD describes Boot/Operate in Section 3.6 - in the Top-Level Design. Additional details are also provided in Sections 4.1.3.||11/12/1999||3||02/01/2000||CLOSED|
|38||DCE SDD: Section: 184.108.40.206||MON51 Task||The detailed design for the serial port should discuss how the DCE FSW is designed such that removing the "serial port driver" and NOT modifying the code will NOT adversely affect operation of the FSW.||The Serial I/O is not presently baselined for the DCE FSW. However, a place-holder for it is mentioned, given that it existed in the FUSE design - and if needed for Ground Testing - it will be included for COS. The Serial I/O Port is described only briefly in Sections 220.127.116.11 and 4.3.1 of the revised DCE SDD.||11/12/1999||122||02/29/2000||CLOSED|
|39||DCE SDD: Figure 01||CNTR label in Figure 1||Change 'CTR A' and 'CTR B' in Figure 1 to 'CNTR A' and 'CNTR B'. (CTR could be confused with Controller, whereas CNTR is more clearly an abbreviation for Counter.)||N/A. New drawings exist in revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|40||DCE SDD: Section: 4.3.2||Software Tool Output Files||Remove the word 'FUSE' from the description of the .CMD files.
Add and describe the .ABS file format (as this is the one that will be used by the CS and stored in MEB EEPROM.)
(Accidentally assigned to Rob. Has been reassigned to Daniel. -KRB)
|Described in Section 5.2.1||11/12/1999||3||02/01/2000||CLOSED|
|41||DCE SDD: Section: 4.4.3||Use of the word 'State' to describe DCE FSW Configuration||Scrub Document - especially material in Section 4.4.3 - and be consistent in the use of the term 'State'. Also, because the word 'State' is used to mean specific operational States in other HST documents (e.g., DM-05), perhaps using a different word, like 'configuration' or 'status' would be better suited for the DCE SDD.||Both Top-Level and Detailed Design Sections have been entirely rewritten to improve both the content and format of the DCE SDD. Attempts were made to use consistant terminology within the document, and w.r.t. other HST Documents.||11/12/1999||122||02/29/2000||CLOSED|
|42||DCE SDD: Section: 4.4||Figure 5||Either combine the pertinent information in Figures 4 & 5 and keep the resulting figure in the Data Flow section, or move Figure 5 to the Control Flow section and expand the existing flow control info.||Updated DCE SDD contains new figures for Control and Data Flow. (See Sections 3.3 and 3.4)||11/12/1999||3||02/01/2000||CLOSED|
|43||DCE SDD: Section: 18.104.22.168||Timer Tick Information||Add that the Timer Tick is based on a 16MHz Clock. (This will help the reader understand why their are 49 ticks per second.)||Section 3.2.10 (Time Management CSC) describes how the 16MHz clock steps down to 49.152 msec per tick.||11/12/1999||3||02/01/2000||CLOSED|
|44||DCE SDD: Section: 4.4.3||Move 'System States' to Detailed Design||Move the information in section 4.4.3 to the detailed design section (Section 5).||State information in previous DCE SDD has been broken down into discussions of Modes (Boot/Operate) and description of how the DCE performs various Tasks. System states, per say, are no longer discussed in the DCE SDD. Instead, DCE State information has been (mostly) relegated to operational documents, such as DM-05 and OP-01.||11/12/1999||122||02/29/2000||CLOSED|
|45||DCE SDD: Section: 5.1||Remove detailed address information from SDD||Remove detailed address information from Section 5.1, and put this information in the appropriate appendices of the FUV Software Users Guide.||Detailed Memory and Register information will be contained in the DCE HW/SW Interface Document (An In Development BATC SER.)||11/12/1999||3||02/01/2000||CLOSED|
|46||DCE SDD: Section: 5.1.2, 5.1.3||Documenting Memory Mapped Registers||Each register should have a description in addition to its name and hardware address. The description should include what data is read/written to the register with a list of all individual bits that make up the register. Bounds on the data that is written/read should also be included. (See CS Hardware/Software Interface SER for example.)||This level of detail has been moved to the DCE HW/SW Interface Document. General descriptions of the registers remain in Section 3.5 of the Top-Level Design, and Sections 4.3 and 4.4 of the Detailed Design.||11/12/1999||122||02/29/2000||CLOSED|
|47||DCE SDD Section: 5.2||Figure 9||Use a symbol other than a 'Square' for the "Hang! Watchdog test" and "(hard reset test message) Wiggle Reset Line, Hard!" items. These items appear to be branch points, and a 'Square' generally isn't used to denote a branch point.||Reset Initialization figure has been replaced in revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|48||DCE SDD: Section: 22.214.171.124||Inspect & Change Task - Serial Port||Change "except consume processor cycles" to something more appropriate. (i.e., explain how this code will NOT cause adverse effects in the flight system where the Serial Port is removed.)
See AI #38
|The Serial I/O is not presently baselined for the DCE FSW. However, a place-holder for it is mentioned, given that it existed in the FUSE design - and if needed for Ground Testing - it will be included for COS. The Serial I/O Port is described only briefly in Sections 126.96.36.199 and 4.3.1 of the revised DCE SDD.||11/12/1999||122||02/29/2000||CLOSED|
|49||DCE SDD: Section: 188.8.131.52.2||Behavior of Door and Door Task if Reset||Need to explain what happens to Door and Door Task if a Reset occurs in the middle of a door move. Will the 3 minute timer still work? Will the door stop?||The internal DCE procedure Safe Controls is executed in all DCE resets (be they complete or minimal.) The Safe Conrols procedure turns off door motor power, sets door direction to STOP, resets door end switch overrides, shuts off AUX Power, etc... (See Section 184.108.40.206 for a complete description.) Bottom Line: The Door is stopped. The 3 minute timer deactivated. If this occured during a door motion, the door would be stopped in mid-motion.||11/12/1999||3||02/01/2000||CLOSED|
|50||DCE SDD: Section: 220.127.116.11||Counters||Remove the word 'output' from the first sentence of this subsection. Describe where the counters are in memory. Reference the subsection on counters in data flow (18.104.22.168), and describe how counters data flows.||Counters are now described in Section 22.214.171.124, and they can be seem in the Figure 3.5-1. The are referenced again in Section 126.96.36.199 - but mostly as a pointer to the DCE HW/SW Interface Document (currently In Development as a BATC SER.)||11/12/1999||112||02/29/2000||CLOSED|
|51||DCE SDD: Section: 4.3.2||Software Tools||Add a pointer to Section 6.2 which describes the particular software used for the DCE FSW.||N/A. Add this information is now contained in Section 5 of the new DCE SDD. Note: A AI #5 for the revised DCE SDD has been generated to cover issue of Symbol Table information in ABS files.||11/12/1999||3||02/01/2000||CLOSED|
|52||DCE SDD: Section: 188.8.131.52||Incomplete Sentence||The first sentence is not a complete sentence. e.g., Add the phrase "The door latch is ..." to the beginning to make it a complete sentence.||N/A - sentence does not exist in revised DCE SDD. Door information has been completely rewritten. Revised DCE SDD contains detailed door information in the Door Task (Section 184.108.40.206), and in Door Commands (Section 220.127.116.11.4). There is also top-level information on the Door Control CSC (Section 3.2.7), on Hardware Interfaces (Section 3.5).||11/12/1999||3||02/01/2000||CLOSED|
|53||DCE SDD: Section: 18.104.22.168||Remove extraneous text||Remove the last two words from the description. (Take out the comma and the "among others".||N/A - sentence does not exist in revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|54||DCE SDD: Section: 5.1||Description of Hardware Terms||Change the word "wiggle" to "pulse".
Change "bitbanging" to a description which explains the implementation of a 3-wire interface. e.g., two 8051 I/O lines act as a synchronous bus (data & clock) connected to all digitizers. Additional 8051 I/O lines (one per digitizer) are used to select only the specific digitizer being queried.
|N/A - sentence does not exist in revised DCE SDD.
Detailed, Hardware information regarding the 3-wire interface has been moved to the DCE Hardware/Software Interface Document (currently In Development as a BATC SER.)
|55||DCE SDD: Section: 22.214.171.124.4||Functions for Inspect & Change Task||Instead of saying "Some commands don't work", say instead that "only a subset of MON51 commands are implemented." Describe (here or elsewhere) which commands are implemented.||The Serial I/O is not presently baselined for the DCE FSW. However, a place-holder for it is mentioned, given that it existed in the FUSE design - and if needed for Ground Testing - it will be included for COS. The Serial I/O Port is described only briefly in Sections 126.96.36.199 and 4.3.1 of the revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|56||DCE SDD: Section: 5.2.3||Vague Reference||188.8.131.52.1: "... some sequence like ...". These are 3 very vague words. State what the design is.
184.108.40.206.3: "... pretty much ...". Ditto.
|N/A - sentence does not exist in revised DCE SDD.
ISRs are discussed in Section 4.2.4 of the revised DCE SDD.
|57||DCE SDD: Section: 220.127.116.11.2||CRP Task||The statement that "... this task may optionally resume..." is very vague. State what actually happens, and the condition(s) under which it actually happens.||CRP Task is described in Section 18.104.22.168 of the revised DCE SDD. (Also, the autonomous recovery option - which lead to the vague wording mentioned in this AI - has been removed in the COS Design.)||11/12/1999||3||02/01/2000||CLOSED|
|58||DCE SDD: Section: 22.214.171.124.5||Inspect & Change Task - Cut and Paste Error||The Text in this section is identical to the text in section 126.96.36.199.5 - looks like a cut and paste error.||NA - Sentence does not exist in the revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|59||DCE SDD: Section: 188.8.131.52||Watchdog Reset Routine||In the third paragraph and the diagram which follows: Show the reset routine for COS, not for FUSE/DPU.||Resets and Initializations are described in Detail in Section 4.2.2 of the revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|60||DCE SDD: Section: 5.1.5||PROM Memory||Make "0-7FFF 0-3FFF" consistent with Figure 2 (Memory Map.)||Memory Map drawings have been redone in the Revised DCE SDD. New drawings are Figure 4.1-1 and 4.4-1. These are consistant with their addressing information. (Note: Detailed Memory Map information will be provided in the DCE HW/SW Interface Document - which is In Development as a BATC SER.)||11/12/1999||3||02/01/2000||CLOSED|
|61||DCE SDD: Section: 184.108.40.206||PHD||A final sentence should be added to this section, which reads "The slice regions are overwritten with zeros after every housekeeping ..."
(Consult with Ira for exact phrasing, I couldn't read handwriting. -KRB)
|N/A - revised DCE SDD does not contain an analogus section. PH Data is now described in Section 220.127.116.11, and again (briefly) In Sections 4.3.1 and 4.3.2. The hardware specific information - for which this AI was orignially written - will be covered in the DCE HW/SW Interface Document, currently In Development as a BATC SER.||11/12/1999||3||02/01/2000||CLOSED|
|62||DCE SDD: Section: 18.104.22.168||PH-Histograms||1st sentence says there are 128 bins; 2nd sentence says there are 2 bins. Suggest that 2nd sentence be modified to say "There are two sets of PH-Histogram bins, one set of 128 bins for MCP segment A, the other set of 128 bins for MCP segment B."||PH Data is now described in Section 22.214.171.124. (Note: There wording in 126.96.36.199 is similar enough to the original DCE SDD that I will leave this AI in the APPROVAL stage until the revised DCE SDD is reviewed.)||11/12/1999||102||03/01/2000||CLOSED|
|63||DCE SDD: Section: 188.8.131.52||PH-Histrograms||This section should indicate that, on a bin by bin basis, only the number of photons detected since the last housekeeping report are reported out in the next housekeeping packet. Suggested wording might be: "... that represent the total number of photons detected since the last housekeeping report, ...".||PH Data are described in Section 184.108.40.206 of the revised DCE SDD. The process of reading and clearing the PH data is described in the Housekeeping Task - Section 220.127.116.11. Hardware-level discussions of the PH Data have been moved to the DCE Hardware/Software Interface Document (which is In Development as a BATC SER.)||11/12/1999||102||03/01/2000||CLOSED|
|64||DCE SDD: Figure 04||Simplified Data Flow Diagram||The flow "telemetry" occurs twice on the right side of the diagram. I suggest changing the upper occurrence to "photon event words", and changing the lower occurrence to "housekeeping".||N/A. This figure is no longer part of the DCE SDD. Control Flow and Data Flow diagrams are not Fig 3.3-1 and Fig. 3.4-1, respectively.||11/12/1999||3||02/01/2000||CLOSED|
|65||DCE SDD: Section: 4.1.2||Hardware Components||This section reads like stream-of-consciousness; rewrite in complete sentences.
"Intent" seems vague - what is the design?
"Partial Von Neumann architecture" is a computer-science concept that may have no place in a design document unless clearly defined - including forward pointers to section(s) in this document where this is described elsewhere.
|Hardware infromation has been entirely rewritten. Top-level information now exists in Section 3.5 (Hardware Interfaces). Detailed-Design information is in Section 4.3 (Internal Hardware Interfaces) and Section 4.4 (Processing Hardware). Bit-level hardware descriptions have been moved to the DCE HW/SW Interface Document (which is In Development as a BATC SER.)||11/12/1999||102||03/01/2000||CLOSED|
|66||DCE SDD: Section: 18.104.22.168||Ports||This section describes the digitizer interface as a synchronous serial port. Is this the only port? If there are others, why single out this one?||8051 Ports are now described in detail in Section 4.3.1 of the revised DCE SDD. Bit-level hardware descriptions of ports been moved to the DCE HW/SW Interface Document (which is In Development as a BATC SER.)||11/12/1999||102||03/01/2000||CLOSED|
|67||DCE SDD: Figure 01||H/W- S/W Interface Description||Figure 1 lists memory-mapped I/O address range, in general. What's needed is a complete memory-map on an address-by-address basis; for each memory mapped I/O address location, give read/write status, bit descriptions, unused bits and what happens (or not) if they are toggled - ask for a copy of the CS H/W - S/W I/F Document for an example of what's needed. This kind of information is also needed for ports, and control bits in the control registers.||Bit-level hardware descriptions have been moved to the DCE HW/SW Interface Document (which is In Development as a BATC SER.)||11/12/1999||3||02/01/2000||CLOSED|
|68||DCE SDD: Figure 01||RAM addresses||Make RAM address range consistent with Figure 2 (Memory Map). Make sure these are consistent with information in sections 5.1.x
Remove 0-1FFF in first RAM block. Remove PROM ON Block.
|Memory Map drawings have been redone in the Revised DCE SDD. New drawings are Figure 4.1-1 and 4.4-1. These are consistant with their addressing information. (Note: Detailed Memory Map information will be provided in the DCE HW/SW Interface Document - which is In Development as a BATC SER.)||11/12/1999||3||02/01/2000||CLOSED|
|69||DCE SDD: Figure 09||Text in Figure 9||Remove the "message" information from this diagram. (There is no serial port in flight.) Also, use the term 'Hardware' instead of 'Hard', when you mean a hardware reset.||DCE Reset diagram has been redone in the revised DCE SDD. (See Figure 4.2-1).||11/12/1999||3||02/01/2000||CLOSED|
|70||DCE SDD: Section: 4.2.2||Internal Registers||Rewrite the second and third sentences to more clearly define the registers used - and not used - by the 8051.||Internal 8051 Registers are described in detail in Section 4.3.1 of the revised DCE SDD.||11/12/1999||3||02/01/2000||CLOSED|
|71||DCE SDD: Section: 22.214.171.124||RAM||1. Change 0x4000 to 0x3FFF.
2. Reword - remove phrase "somewhat arbitrarily".
3. Typo in the word "upon".
4. Describe the memory initialization in the last two sentences. Who initializes, S/W or H/W? Is the 32K RAM ever initialized?
5. Include forward pointers to POR and Watchdog Resets in Section 5.2.1.
|Information formerly contained in 126.96.36.199 of the original DCE SDD has been completely rewritten. Information can now be found in Sections 4.1.2, 4.1.3, 4.2.2, .and 4.4.2.||11/12/1999||3||02/01/2000||CLOSED|
|72||DCE SDD: Section: 1.1||Identification Description||1st sentence, change the word 'describes' to 'describing'.||N/A. Section 1.1 rewritten in revised DCE SDD||11/12/1999||3||02/01/2000||CLOSED|
|73||DCE SDD: Section: 1.2||Document Overview and TOC||Make certain that Section Descriptions in the Document Overview match the Table of Contents.||Done||11/12/1999||3||02/01/2000||CLOSED|
|74||DCE SDD: Section: 5.2.2||Task Algorithms||Include a figure (like Figure 11) for each Task defined in section 5.2.2||Each Task in the revised DCE SDD now has a Processing Logic description, and a Logic Flow diagram.||11/12/1999||3||02/01/2000||CLOSED|
|75||DCE SDD: Section: 4.3||State Diagrams||Include a State Diagram and Description for each Task in the DCE system. (As a minimum, everything in Figure 10 should be so described.)||Figure 10 is reproduced in Figure 3.3-1 of the revised DCE SDD. Further, each Task (and ISR) in Figure 3.3-1 is now described individually, including both a Processing Logic description, and a Logic Flow diagram. State information, however, has been left to operational documents - such as DM-05, and OP-01. This is to avoid confusion in discussing States at a component level - which often differ from how States are used at an operational level.||11/12/1999||110||03/01/2000||CLOSED|
|76||DCE SDD: Section: 5.1.4||Memory Allocations||Explain, in more detail, the concept of maintaining memory allocations.||Described in the revised DCE SDD in Sections 4.1.2, 4.1.3, and 4.4.2.||11/12/1999||110||03/01/2000||CLOSED|
|77||DCE SDD: Section: 188.8.131.52||Door States||Add an additional state diagram for the FUV Detector Door - include the difference between Motor and Actuator states.||Door information has been completely rewritten. Revised DCE SDD contains detailed door information in the Door Task (Section 184.108.40.206), and in Door Commands (Section 220.127.116.11.4). There is also top-level information on the Door Control CSC (Section 3.2.7), on Hardware Interfaces (Section 3.5). State information, however, has been left to operational documents - such as DM-05, and OP-01. This is to avoid confusion in discussing States at a component level - which often differ from how States are used at an operational level.||11/12/1999||110||03/01/2000||CLOSED|
|78||DCE SDD: Section: 18.104.22.168||RAM initialization and Resets||Explain differences in RAM between Power ON and Power ON Reset. (e.g., 32K RAM initialization.)
See AI #71.
|Description of Resets and Initializations have been completely rewritten in the revised DCE SDD. Information is now in Section 4.2.2||11/12/1999||110||03/01/2000||CLOSED|
|79||DCE SDD||Boot/Operate Capabilities||A description needs to be added discussing those tasks and capabilities which are functional in BOOT and those that are functional in OPERATE.
See AI# 36, 37.
|Boot and Operate information has been completely rewritten in the revised DCE SDD. Sections 3.6, 4.1.3, and portions of 4.2 now contain information of Boot/Operate. In short, Boot is a subset of Operate. There are NO functions in Boot which are not also present in Operate.||11/12/1999||110||03/01/2000||CLOSED|
|80||DCE SDD: Figure 02||Figure 2||Update Figure 2 with the following information.
1. Include Harvard and Von Neumann labels appropriately on Memory Map. (Include, in the figure caption, pointers to section(s) in text which describe these terms.)
2. Change diagram to remove dotted line between Code/Data for 8000-FFFF (this will help show that above 7FFF, Code and Data are the same.)
3. Add solid line under 'variables' and 'samples' to show that these areas occupy specific regions in LCA and UCA. (Exact placement of line is not important, and you can state as much if you are concerned about someone over-interpreting the exact size of the 'variable' and 'sample' areas from this figure.)
|In the revised DCE SDD, Figure 2 has been replaced by Figure 4.1-1, Figure 4.4-1 and Figure 4.4-2. In addition, hardware specific information (aside from general memory addresses) has been moved to the DCE Hardware/Software Interface Document (currently In Development as a BATC SER.)||11/12/1999||110||03/01/2000||CLOSED|
|81||DCE SDD: Section: 2.2||Document Reference||The 'MON51 Manual', referred to in Section 22.214.171.124.4, should be added to the DCE Hardware Documentation List.||Section 2.2 of the revised DCE SDD now contains an appropriate list of COS Documentation and COTS Documentation.||11/12/1999||105||03/01/2000||CLOSED|
|82||DCE SDD: Section: 4.4.2||Event Flow Paragraph Layout||Change Figure 5 Label to "DCE Events Diagram", or "DCE Control Flow Diagram". Change 4.4.2. Label to "DCE Events" or "DCE Control Flow". Make subparagraph headings in 4.4.2 agree with Figure 5. Move the entire section of 4.4.2 into section 4.5.||Updated DCE SDD contains new figures and text for Control and Data Flow. (See Sections 3.3 and 3.4).||11/12/1999||105||03/01/2000||CLOSED|
|83||DCE SDD: Section: 126.96.36.199||Commands/Housekeeping||Add a reference to the commands documented in Appendix B of DM-05. Add a section to 4.4.1 for housekeeping and include a reference to the FUV Detector ICD.||DCE Commands are now fully described in Section 4.2.8 (including a reference to Appendix B of DM-05.) Housekeeping Items are called out in the FUV ICD, and will be further described in a series of UCB SERs - which will be folded into DM-02 and DM-14.||11/12/1999||105||03/01/2000||CLOSED|
|84||DCE SDD: Section: 4.4||Data Flow Paragraph Layout||Combine 4.4.1 & 4.4.4 into one section called "Data Flow" and make sure there is one subparagraph matching each labeled data flow in Figure 4.
Move 188.8.131.52 and 184.108.40.206 to another section - Either under 4.4.2, or in Hardware section of detailed design.
|Revised DCE SDD contains new sections on Control Flow and Data Flow (see Sections 3.3 and 3.4) Information on Serial Ports and Timer(s) have been moved into individual sections. (See Sections 3.2.10, 3.5, 4.2.9, and 4.3).||11/12/1999||105||03/01/2000||CLOSED|
|85||DCE SDD: Section: 220.127.116.11||RAM and Resets||Delete last two sentences of Section 18.104.22.168. (This is a hardware section). Defer discussion of resets to to Section 5.2.1||Hardware information is now discussed in Section 3.5, and again in 4.3 and 4.4. Specific Hardware/Software issues have been delegated to the DCE HW/SW Interface Document (currently In Development as a BATC SER.) Reset information is now contained inSection 4.2.2.||11/12/1999||105||03/01/2000||CLOSED|
|86||DCE SDD: Section: 22.214.171.124||Digitizers and Resets||Delete last sentence of Section 126.96.36.199. Defer Discussion of Resets to Section 5.2.1.||Digitizer Information is now in Section 3.5, and briefly mention again in Section 4.3. Reset information is now contained inSection 4.2.2. Specific Hardware/Software issues have been delegated to the DCE HW/SW Interface Document (currently In Development as a BATC SER.)||11/12/1999||3||02/03/2000||CLOSED|
|87||DCE SDD: Section: 188.8.131.52||HSK TLM and CMD conversion factors||Determine where the Conversion Factors for FUV Detector HSK TLM and CMDs are documented, and describe this in 184.108.40.206.
Was originally assigned to Geoff Gaines. See response written by KRB below. (Section 220.127.116.11 can point to DM-14.)
|After discussions with Grant Blue and Rob Lampereur, on 11/01/1999, it was felt that a UCB SER (or the equivalent) was the best place for the HSK TLM and CMD conversion factors to be documented. When UCB issues this SER, the values can then be rolled into the BATC database for inclusion into DM-14. (-KRB 11/01/1999)||11/12/1999||105||03/01/2000||CLOSED|
|88||DCE SDD: Section: 1.4||Description of ICD for FUV Detector Subsystem||In section 1.4, refer to the FUV Detector Subsystem ICD as such, don't just say "the ICD".||In revised DCE SDD, all occurances (except one - see new AI #1), correctly refer to the FUV Detector Subsystem ICD as the FUV ICD.||11/12/1999||3||02/03/2000||CLOSED|
|89||DCE SDD: Section: 18.104.22.168||Counter Descriptions||Add full descriptions of all the different counters. (e.g., Only the FEC is mentioned here, and it is not described.)||Counters are described in Section 22.214.171.124. They will also be described in the DCE HW/SW Interface Document. (Currently In Development as a BATC SER.) See AI#2 of revised DCE SDD.||11/12/1999||3||03/28/2000||CLOSED|
|90||DCE SDD: Section: 126.96.36.199||PHD Read/Clear Rate||Describe the rate and which PHD data is read-out and cleared.
Add descriptive test to explain exactly how the PHD data are cleared when the data is transferred with HSK.
|PH Data are described in Section 188.8.131.52 of the revised DCE SDD. The process of reading and clearing the PH data is described in the Housekeeping Task - Section 184.108.40.206. Hardware-level discussions of the PH Data have been moved to the DCE Hardware/Software Interface Document (which is In Development as a BATC SER.)||11/12/1999||3||03/28/2000||CLOSED|
|91||DCE SDD: Figure 05||Figure 5: Data Flow Diagram||Update Figure 5 in the following fashion:
1. Eliminate the "Background" ellipse. Move the background task(s) under the Main Routine.
2. Recast the diagram so that it agrees with the description of the Command Task Handler in Section 5.2.2, 220.127.116.11 and Figure 10.
|Updated DCE SDD contains new figures for Control and Data Flow. (See Sections 3.3 and 3.4) In addition, each of the Tasks called by the Executive Loop are fully described in their own subsections. See Section 4.2.3 in the revised DCE SDD.||11/12/1999||3||03/28/2000||CLOSED|
|92||DCE SDD: Section: 5.1||DCE Hardware Information||Move the "high-level" information from Section 5.1, and combine it with hardware information found earlier in the document, and put it all in a new section called "Hardware Overview".||Hardware Information is now contained in the top-level design, in Section 3.5 of the revised DCE SDD. Some additional HW information is also contained in Sections 4.3 and 4.4 of the Detailed Design. Much of the specific Hardware information has been moved to the DCE HW/SW Interface Document - which is currently In Development as a BATC SER.||11/12/1999||3||03/28/2000||CLOSED|
|93||DCE SDD: Figure 11||Figure 11 - Timing Info in CRP Algorithm||Update Figure 11 to correctly show the relationship between timing information and the CRP algorithm execution.||The CRP Task description has been updated in the revised DCE SDD. (See section 18.104.22.168.) However, the Task as described in the DCE SDD is NOT what UCB will be implementing. An new action item (#3 for Revised DCE SDD) documents a request for updating the description of CRP - and asks that timing issues of CRP be explained - with regards to Count Rates being updated only once per second.||11/12/1999||3||03/28/2000||CLOSED|
|94||DCE SDD: Section: 22.214.171.124||Use of the term Power-On Reset (POR)||Power On Reset (POR) should NOT be named as such if the result of a POR and a Power ON do not leave the entire FUV "System" in the same state. (Not just with respect to the FSW.)||Descriptions of Resets and Initializations have been completely rewritten in the revised DCE SDD. (See section 4.2.2) The term's "Complete Initialization" and "Minimal Initialization" are preferred for describing the level of initialization that is done upon a DCE Reset. However, because UCB continues to refer to POR for non-"Power ON" events, the term POR has been kept in the revised DCE SDD for continuity.
A New Action Item (AI #6) for the Revised DCE SDD has been generated to track the issue of the term "POR" in the Design Document.
|95||DCE SDD: Section: 4.1||FPGA (Actel) Memory Map Assignments||The current memory map assignments of the FPGA's don't reflect the "final" values. The FPGA's should have their assignments reflected as now understood. If they are likely to be revised, state TBR until final assignments are made.||Updated DCE SDD does not call out specific memory assignments of the FPGAs. Specific H/W information will be described in DCE HW/SW Interface Document (An In Development BATC SER.)||11/12/1999||109||02/29/2000||CLOSED|
|96||DCE SDD: Section: 5.2.1||Continuous Watchdog Reset||Remove the last sentence in the second paragraph of section 5.2.1. The DCE FSW design we are working towards specifically comes up in BOOT with the watchdog timer disabled to avoid this very possibility.||N/A. The section describing Resets and Initializations has been completely rewritten. See section 4.2.2 of the Revised DCE SDD.||11/12/1999||3||02/18/2000||CLOSED|
|97||DCE SDD: Section: 126.96.36.199||HVPS values||List the DAC values as "0 to 5 Volts". List the HV values as "approx. -2000 to -6000 Volts".||Specific conversion values have been left out of the DCE SDD. These values will be documented in UCB SERs, and later folded into DM-05, DM-02, and DM-14.||11/12/1999||3||02/18/2000||CLOSED|
|98||DCE SDD: Figure 11||"Restore HV" Block in Figure 11||The "Restore HV" Block in Figure 11 should not be a DCE FSW task. Recovery from a CRP limit violation should be a ground command, handled in real-time operations.||The autonomous Restore functionality for the CRP algorithm has been removed. The CRP Task described in the DCE SDD is being updated. A new action item (#3) for the revised DCE SDD documents the request to describe the new CRP scheme.||11/12/1999||3||02/18/2000||CLOSED|
|99||DCE SDD: Section: 188.8.131.52.2||HV Ramp Task Events||Event section states: "CRP and CLP can stop ramping or even force HV to the off state." Clarify the differences between CRP and CLP actions - and/or point to section of document that describes these actions.||CRP, CLP and HV Ramp Tasks have been completely rewritten in the revised DCE SDD. (See sections 184.108.40.206, 220.127.116.11 and 18.104.22.168 in the revised DCE SDD.) The actions of CRP and CLP - and how they interact with the HV Ramp Task - are described in greater detail.||11/12/1999||113||02/29/2000||CLOSED|
|100||DCE SDD: Section: 22.214.171.124||Current Limit Protection Task||Clarify the distinction between the CLP task reporting a diagnostic and shutting off the HVPS.||The CLP Task has been completely rewritten. See section sections 3.2.4 and 126.96.36.199 of the revised DCE SDD.||11/12/1999||113||02/29/2000||CLOSED|
|101||DCE SDD: Section: 188.8.131.52||Door Operations and HV||Prevent Door Operations if High Voltage is On.||This CARD item will be handled at the operations level. (See DM-05.) There is no need to burden the DCE FSW with added safety checking for something that should NEVER be done operationally.||11/12/1999||3||02/18/2000||CLOSED|
|102||DCE SDD: Section: 1.3||COS FSW Overview||Add the word "monitoring" to the list of resources in the first sentence.||N/A. The DCE FSW Overview has been completely rewritten. See section 3 of the revised DCE SDD.||11/12/1999||3||02/18/2000||CLOSED|
|103||DCE SDD: Section: 4.6||Design Philosophy - "Energy"||The description of "energy" is confusing. Consider replacing with something like:
Commands that could severely degrade the detector require a separate software interlock to protect the detector. These commands include HV and Door commands. The interlock must be enabled to send these commands. To protect the detector, the interlock does NOT need to be enabled to transition the detector to a "safer" state. Commands to turn HV or Door Power OFF or to ramp HV down can be sent at any time.
|The section describing commandable energy has been completely rewritten. See section 184.108.40.206 of the revised DCE SDD.||11/12/1999||107||02/29/2000||CLOSED|
|104||DCE SDD: Section: 220.127.116.11||Power On Reset (POR)||Paragraph 1: Change "known" state to "Boot" state.
Paragraph 2: Don't use the term "everything but", instead say "The POR initialization fills the stack w/ zeros, ...". Finally, the last sentence of the 2nd paragraph implies that commands can be sent during a POR?! Is this true? Are commands actually processed normally during a POR?
|Initialization and Resets descriptions have been completely rewritten. See sections 3.2.1 and 4.2.2 of the revised DCE SDD.||11/12/1999||107||02/29/2000||CLOSED|
|105||DCE SDD: Section: 18.104.22.168.x||CRP Task Algorithm||In 22.214.171.124.3 and 126.96.36.199.4, remove reference that Figure 11 was made for FUSE.||Description of CRP Task has been completely rewritten inthe revised DCE SDD. (See Section 188.8.131.52)||11/12/1999||107||02/29/2000||CLOSED|
|106||DCE SDD: Section: 184.108.40.206||CRC Checking Task||Link-list of data structures: How are the items in this linked-list chosen? Where are the details of the list documented? Is there a separate HSK item for EACH item on the list?
Which CMDS force the CRC-checking machine to a known state?
|CRC Task is described in section 220.127.116.11 of the revised DCE SDD. Additional information can be found in the Background Monitoring CSC (section 3.2.8).
Resetting the DCE, or executing the Executive Loop Initialization Sequence (e.g., via a JUMP command) will reset the CRC Task to begin CRC checking at the default starting address.
|107||DCE SDD: Section: 18.104.22.168.5||Complete Sentences||Last two sentences in 22.214.171.124.5 are not. Add subjects to make them complete sentences.||Command Handler Task description has been completely rewritten, and can be found in section 126.96.36.199 of the revised DCE SDD.||11/12/1999||107||02/29/2000||CLOSED|
|108||DCE SDD: Section: 4.4.3||Task State Descriptions||In sections 188.8.131.52 - 184.108.40.206, all the possible states for each task are only listed parenthetically. All states must be described clearly - with one or two sentences for each state.||State information in previous DCE SDD has been broken down into discussions of Modes (Boot/Operate) and description of how the DCE performs various Tasks. System states, per say, are no longer discussed in the DCE SDD. Instead, DCE State information has been (mostly) relegated to operational documents, such as DM-05 and OP-01.
|109||DCE SDD: Figure 07||Event Labels on HV State Diagram||Add event labels for each arrow on the HV State Diagram.||State information in previous DCE SDD has been broken down into discussions of Modes (Boot/Operate) and description of how the DCE performs various Tasks. System states, per say, are no longer discussed in the DCE SDD. Instead, DCE State information has been (mostly) relegated to operational documents, such as DM-05 and OP-01.
Information about the FUV Detector High Voltage can now be found in: The Detector Control CSC (section 3.2.6), the HV Ramp Task (section 220.127.116.11), and in the descriptions of the HV Commands (section 18.104.22.168.3)
|110||DCE SDD: Section: 22.214.171.124||HVState "Unknown"||Change the HVState of "Unknown" to "HVSet".||State information in previous DCE SDD has been broken down into discussions of Modes (Boot/Operate) and description of how the DCE performs various Tasks. System states, per say, are no longer discussed in the DCE SDD. Instead, DCE State information has been (mostly) relegated to operational documents, such as DM-05 and OP-01.
Information about the FUV Detector High Voltage can now be found in: The Detector Control CSC (section 3.2.6), the HV Ramp Task (section 126.96.36.199), and in the descriptions of the HV Commands (section 188.8.131.52.3)
|111||DCE SDD: Section: 184.108.40.206||DoorState "Unknown"||Change the DoorState of "Unknown" to "Position Unknown".||State information in previous DCE SDD has been broken down into discussions of Modes (Boot/Operate) and description of how the DCE performs various Tasks. System states, per say, are no longer discussed in the DCE SDD. Instead, DCE State information has been (mostly) relegated to operational documents, such as DM-05 and OP-01.
Information about the FUV Detector Door can now be found in: The Door Control CSC (section 3.2.7), the Door Task (section 220.127.116.11), and in the descriptions of the Door Commands (section 18.104.22.168.4)
|112||DCE SDD: Section: 22.214.171.124||Naming of RAM Devices||Use names (other than sizes, e.g. 32K or 8K) to describe the RAM devices in the DCE. Use these names consistently throughout the DCE SDD.||The RAM devices have retained their names 8K and 32K - for the reason that 8K and 32K are descriptive of the amount of RAM that is usable in the current design. Efforts have been made to describe this concept in greater detail. (See section 126.96.36.199 of the revised DCE SDD.)||11/12/1999||112||02/29/2000||CLOSED|
|113||Revised DCE SDD - Section: 4.2.9||Incorrect Labeling of FUV ICD||In the sentence, "See the DCE ICD section 8.5 Packet Protocol for more information.", the word "DCE" should be replaced with "FUV".||Sentence corrected.||03/01/2000||CLOSED|
|114||Revised DCE SDD - Section: 188.8.131.52||Counters||Last sentence in Section 184.108.40.206 says that a complete description of the counters is contained in the FUV ICD. I find no mention of Counters in the ICD, other than in Figure 3.1-3 - which is duplicated in full as Figure 3.5-1 in the DCE SDD. So, either remove the reference and describe counters in full in the DCE SDD - or, correct the reference and point to the proper controlled document where counters are described in detail.||Counter Description should be contained in DM-02, not the DCE SDD. DCE SDD should be updated to point to this document.||03/01/2000||OPEN|
|115||Revised DCE SDD - Section: 220.127.116.11||Count Rate Protection (CRP) Task||Update the CRP Task algorithm to show how the new, UCB algorithm will be implemented. Be certain to describe how Count Rates - which are updated once per second - influence the timing of the CRP algorithm.||See CRP Memo Written by John Vallerga.||03/01/2000||OPEN|
|116||Revised DCE SDD - Section: 18.104.22.168.3||PROM Enable / Memory Bank Switching||Drop the concept of the PROM Enable bit being used for Memory Bank Switching. It does not work - and causes a DCE Hang. Change would require a Flight Board modification (possibly an Actel redesign). Options exist to "fix" in software - but require the initialization sequence to "copy" ISR instructions to fixed locations in RAM.||03/01/2000||OPEN|
|117||Revised DCE SDD - Section: 5||Symbol Table Information in ABS files||The SDD lists that the abs file will contain the executable and the symbol information. It was mentioned at the review that the current set of tools does not provide the symbol information. Section 5 of the new document needs to be updated with the new tool which will provide the symbol information.||03/01/2000||OPEN|
|118||Revised DCE SDD - Section: 22.214.171.124||POR Terminology||Change the POR Terminology in the revised DCE SDD to "Complete Initialization" whenever the Reset is SW in nature. Use the term POR to refer to hardware, power-on resets only. (See AI #94 from the Original DCE SDD.)||03/01/2000||OPEN|
|119||Revised DCE SDD - Section 126.96.36.199.1||Command Handling Handshake using Interrupt Enable||Remove enable interrupts from bottom of Processing Logic||Done||08/09/2000||3||08/09/2000||CLOSED|
|120||Revised DCE SDD - Section 188.8.131.52||Ramp Task Timing Source is Timer ISR||Timer ISR should implement Ramp Tick flag, faster than 1 per second... (Ramp Task)||OPEN|
|121||Revised DCE SDD - Section 184.108.40.206||CRC Regions||Add text describing the CRC Regions that are examined by the Background CRC Task. Some notes on adding, and/or changing the regions would be very useful. Also, add text on how the regions are chained together in a linked data-structure, and how this chaining defines the sequence of how the regions are examined.||OPEN|
|122||Revised DCE SDD - Sections 220.127.116.11 & 18.104.22.168||Command Packet Format and Commanded Reset||As per the Command Traffic ISR Logic Flow - when the MSB=1 and the remaining Bits are NOT all zero, then interrupts remain disabled and all future commands are blocked out. Is this a code or a document error?||Logic Flow Diagram has been updated. Needs to be updated in DCE SDD.||08/09/2000||OPEN|
|123||Revised DCE SDD - Section 7||Acronyms||Add the following items to the Acronym List:
HOP, MCS, GALEX, FEC, DEC, BBIT, MUX, ADC, SCC, LED, iRMK, OS, ISR, POR, GPC, HSK, CRP, LCA, UCA, SIMM
|124||Revised DCE SDD - Section 22.214.171.124||Memory Map - Patchable Constants||Add a Patchable Constants are of memory where the FSW variables which are changable/adjustable on-orbit are stored. This area should be separate from the code area. An example of a variable in this category is the consecutive out-of-limits counter in the Current Limit Protection task. (Now has a value of 20.)||OPEN|
|125||Revised DCE SDD - Section 126.96.36.199||Figure 4.4-2||Add Patchable Constants area to the Memory Map.||OPEN|
|126||Revised DCE SDD - Section 188.8.131.52||Initialization Sequences||Put the Initialization Sequences (Complete, Minimal and Executive Loop) in a Table - to make it easier to see the differences bewteen these Initialization processes.||OPEN|
|127||Revised DCE SDD - Section 4.4.4||DCE Reset Initialization - Figure 4.2-1||Update the Figure to include the Watchdog Reset Counter (and the corresponding POR in the event of 255 continuous reset events.)||OPEN|
|128||Revised DCE SDD - Section 3.6.1||DOOR/HV Operations Disabled after Reset||Add to the Initialization Function a bullet statement which indicates that hardware functions (e.g., Door Operatios, HV Operations, Digitizer Operations) are disabled after a reset.||OPEN|
|129||Revised DCE SDD - Sections 3.6.1 & 3.6.2||Functions Lists||Put functionality into a table to show which funtions are enabled at BOOT vs OPERATE. This would make it easier to see differences/commonality.||OPEN|
|130||Revised DCE SDD - Section 184.108.40.206||Redundant Command Channels||Add a description that the Command Channel which is used (i.e., A or B) is controlled by which MEB is being used for commanding.||OPEN|
|131||Revised DCE SDD - Sections 3.4 & 3.5||Interrupts||Add an Interrupt Table & Identify how each is handled.||OPEN|
|132||Revised DCE SDD - Section 2||Applicable Documents||Include the GSFC PAR Document as one of the Other Applicable Documents||OPEN|
|133||Revised DCE SDD - Section 220.127.116.11||External Reset Line||Under Miscellaneous -
The External Reset Line is controlled by the CS, and is NOT a GSE only function.
|134||Revised DCE SDD - Section 18.104.22.168||Redundant Command Registers||Provide a function to allow the DCE FSW to ignore the unselected command input register A or B.||OPEN|