COS DCE Boot FSW changes from v01.12 to v01.13

1. Bootmain.a51 – Add two “delta CRC” words to the image, one at address 0x17FE and one at 0x1FFE. These two words force the CRC for the two PROM regions – 0x0000-0x17FF and 0x1800-0x1FFF – to each be 0xC001. This change is made to conform to the Operate Code image which will also have preset CRCs for its various regions (though different from the Boot CRC).

2. Bootmain.a51 – Status Bits 4 and 5 were reversed. Status Bits 4 now points to CONTROLS2 (locked register) and Status Bits 5 now points to CONTROLS1 (unlocked register). Since these two control registers are zeroed in Boot and are never changed, this FSW change is somewhat cosmetic. However, if one were to write directly to the CONTROLS1 and/or CONTROLS2 registers from within Boot, the wrong status would be reported in housekeeping.

COS DCE Boot FSW changes from v01.09 to v01.12

1. Bootmain.a51 – The Primary and Secondary command ISRs now are set to HIGH priority and they use register bank 3 in order that they not conflict with Timer0 which is still at LOW priority (and, hence, can be interrupted itself) and which uses register bank 1. This was change was made in an attempt to correct an upload bug. Though this change was found to be unnecessary for fixing that bug, it was retained for similarity to Operate code which needed the change to handle commanding from the Berkeley GSE.

2. Bootmain.a51 – For Power-On Resets, a new subroutine, ‘INIT_HARDWARE’, is called right after the patchable constants are copied. This new subroutine places various of the digitizer (TDC) DACs into initial configuration.

3. Bootmain.a51 – Command LFDUPLOD now called ‘INIT_CRC’ along with its call to ‘CLEAR_OLD_CRCS’ in order to prevent upload commands from causing background CRC comparison errors.

4. Bootmain.a51 – A new command, ‘LFDRSTA’, which initialized the ACTEL counters, was added to the command list and is implemented via the subroutine ‘DCE_LFDRSTA’. Its command opcode is ‘FA’ and it takes no arguments.

5. Bootmain.a51 – Subroutine ‘safe_controls’ now shuts off STIMS and resets VMAX and VSET to zero (both segments).

Note: Item 3 was the reason that a revision to Boot was undertaken. The other changes were made since it was convenient to do so.

COS DCE Boot FSW changes from v01.07 to v01.09

1. bootmain.a51 – Eliminated ‘secs_flag’ since all calls to one-second events are performed right in the Timer0 ISR. For boot mode, there are no such events, but this allows us to not interrupt the background CRC and housekeeping building tasks for the one-second events.

2. bootmain.a51 – LFDDNLOD now fills the unused portion of the download buffer with character ‘DD’.

3. bootmain.a51 – Subroutines ‘BG_CRC’ and ‘MEMORY_MONITORS’ no longer switch register banks to bank 2. This was unnecessary and so eliminated. This also allows this version of boot code to mirror the operate code in this respect.

4. patchcst.a51 – HST error parameter for diagnostic 02 is now the computed CRC for the upload region (LFMXFER) vice the expected CRC for that region.

5. patchcst.a51 – LFMXFER is now displayed in housekeeping beginning at address 0x17F5 (little-endian).

COS DCE Boot FSW changes from v01.05 to v01.07

1. bootmain.a51 – A/D MUX delays were shortened (though they may still be up to 2.5 msec for each reading) to a default value of 50 μsec per reading. Because of this change, A/D readings no longer share the processor with other tasks. That is, the flags ‘HKP_RESUME’, ‘TIMER1_DONE’, and ‘TIMER1_EDGE’ are gone. When an A/D reading is begun, the boot code stays in a loop waiting until done rather than freeing up the processor for other tasks. This is because no meaningful computations can be made in 50 μsec given the overhead involved in leaving and reentering a subroutine. This considerably simplifies the code and makes the handling of A/D conversions in Operate mode much simpler.

2. bootmain.a51 – As a result of the above change, Timer1 ISR is no longer used. The only interrupts still in use are the two external interrupts for primary and secondary command channels and one timer, Timer0.

3. bootmain.a51 – The four unused ISRs now report diagnostic 31 if entered. The HST error parameter is the address of the ISR vector (i.e., 001Bh, 0023h, 002Bh, and 0033h).

4. bootmain.a51 – Differentiation between Power-on and Watchdog reset is now performed through a 6-byte sequence in external RAM. This change was due to the discovery that the flight 8051 processor does not have the PCON.4 bit which performs this differentiation (as do other variants of the 8051 family).

5. bootmain.a51 – Watchdog reset (LFDRSTW command) no longer toggles the hardware reset line but, rather, enables the Programmable Counter Array’s watchdog timer (the same used when the watchdog is enabled) with a very short timeout. In this way, the watchdog reset command performs in a manner identical to an actual watchdog timeout.

6. bootmain.a51 – Three bits in housekeeping which report door status are cleared to reflect the fact that without auxillary power on, their state is indeterminate.

7. bootmain.a51 – Diagnostics for ROM, Lower Code Area, and Upper Code Area are removed and replaced by Diagnostic 32 – ‘Error in a background CRC area’. The HST error parameter associated with this diagnostic is the region (0-15) in which the error occurred. The CRCs for all 16 regions are reported in housekeeping (now), so the same information is available as before.

8. patchcst.a51 – Background CRC regions were changed to reflect the fact that there is now no distinction between Lower Code Area and Upper Code Area.

9. patchcst.a51 – Items added to housekeeping packet in unused areas: (1) All 16 background CRC values and, (2) Stack high-water mark.

10. patchcst.a51 – Analog items in housekeeping (housekeeping script opcodes 06, 46, and 82) no longer specify the MUX delay time for the particular reading. Rather, two new patchable constants – ‘mMUX_DELAY’ and ‘mADC_DELAY’ – specify the time (multiples of 10 μsec) for MUX delay and ADC conversion time. These two constants control the timing for ALL ADC readings.

COS DCE Boot FSW changes from v01.04 to v01.05

1. patchcst.a51 – default analog MUX delay set at 10 units (approximately 563 msec) for each analog channel.

2. bootmain.a51 – A/D readings (only used in building the housekeeping packet) are now performed in the Timer1 ISR rather than merely having that ISR flag the system that the MUX delay is done and it is time to read the A/D. This cuts down considerably in the variability of the delay time. Analog MUX delays are now measured in multiples of 0.050 msec with overhead of 0.068 msec for all delay time. That is, for a delay counter ‘X’, the MUX delay time is: Time (msec) = 0.050 * X + 0.068, for X=1,2,…,255. For X=0, the A2D reading begins within 0.015 msec of the MUX selection.

3. bootmain.a51 – Tweaked the Timer0 ISR ‘latency’ parameter to achieve finer timing accuracy.

4. bootmain.a51 – Boot code now issues a housekeeping packet upon reset.

5. bootmain.a51 – LFDCOPY command now produces a diagnostic report if length zero is specified.

6. bootmain.a51 – LFDJMPCS now has no parameters. It is redefined as “jump to operate”.

7. bootmain.a51 – Routine ‘BUILD_HKP’ now ensures that the address pointer into the housekeeping packet is within range at the beginning of each script line execution. This prevents the housekeeping script from scribbling more than 255 bytes beyond the end of the housekeeping packet area (which is clear memory and will remain so).

8. bootmain.a51 – removed some unused script opcodes from ‘BUILD_HKP’.

COS DCE Boot FSW changes from v01.03 to v01.04

1. Bootmain.a51 – Properly handle case where no diagnostics occur since last housekeeping packet sent.

2. Bootmain.a51 – Set port bit ‘RAM_BANK’ (P1.6) to ‘1’ vice ‘0’.

3. Bootmain.a51 – Implement a more complete use of event flags for enabling specific tasks in the main executive loop.

COS DCE Boot FSW changes from v01.02 to v01.03

1. Common.inc – Location of patchable constants in CODE space moved from 1000h to 1060h so that the offset to the XDATA location would be a nice, round 1500h, facilitating finding the location of a patchable constant from its CODE space equivalent.

2. Common.inc – DIAG001F was incorrectly given the value 5A1Eh. It has been changed to 5A1Fh.

3. Common.inc – New diagnostics, DIAG0031, was implemented to indicate “Attempt to execute nonexistent ISR”.

4. Common.inc – Mnemonic “C2_UNLOCK” was changed to “C2_LOCK”, indicating that value ‘1’ means that register CONTROLS2 is locked and cannot be read or written. This is a hardware interface change.

5. Common.inc – Mnemonic “CPHDIS” was changed to its hardware name “PHA_DIS”. No polarity change was made in its use, though v01.03 now initializes it to ‘0’ upon reset.

6. Common.inc – Port pin P1.6 defined by the mnemonic “RAM_BANK”, reflecting its use in selecting whether DCE-B RAM chip U8 is banked to addresses 0000-3FFFh or to 4000-7FFFh. In version v01.02, this pin was left in its reset state, ‘1’, but conversation with Geoff Gaines resulted in our agreement that it should be set to ‘0’. RAM_BANK is now cleared to ‘0’ upon reset and is left untouched throughout the rest of Boot code.

7. Common.inc – Mnemonic “CMD_RESET” changed to “ACTEL_RESET” but its polarity was left unchanged. ACTEL_RESET is now performed upon 8051 reset by outputting a value ‘0’, waiting 10 μs, then outputting value ‘1’. Otherwise, the software does not change ACTEL_RESET.

8. Patchcst.a51 – Version number changed to 01.03

9. Patchcst.a51 – Additional elements added to HSTERR_TABLE for the new diagnostic (DIAG0031).

10. Patchcst.a51 – Default analog MUX delay changed from 3 (x 0.384 msec) to 0. This gives a basic 20 μs delay after MUX selection before commanding the A/D converter to begin.

11. Patchcst.a51 – Housekeeping packet changed extensively in accordance with conversations with Geoff Gaines.

12. Bootmain.a51 – removed ‘Requirements question’ and ‘Hardware question’ comments.

13. Bootmain.a51 – removed label ‘BOOT_MAIN_99’ and the ljmp instruction which followed it (per instructions during telecon 10/5/00).

14. Bootmain.a51 – changed some label names in ‘BOOT_MAIN_EXECUTIVE’ for consistency.

15. Bootmain.a51 – Moved call to ‘CLEAR_HKP_PKT’ after completion of building the housekeeping packet rather than after sending the packet. In other words, I now clear it at the earliest opportunity after I have finished using it.

16. Bootmain.a51 – Moved the actual initialization of the housekeeping build from routine ‘PROCESS_COMMAND’ to its own routine called ‘SETUP_TO_BUILD_HKP’ since the contents of that effort was growing.

17. Bootmain.a51 – Implemented the correction to the housekeeping packet so that the five diagnostic messages shown are cleared each housekeeping packet and only those which occurred since the last housekeeping packet are given.

18. Bootmain.a51 – The DCE_LFDUPLOD command now calls routine ‘CLEAR_OLD_CRCS’ so that upload commands will not result in a CRC diagnostic.

19. Bootmain.a51 – Removed the unused ‘FEED_DOG’ routine.

20. Bootmain.a51 – Any HST errors beyond the first 8 received since the last housekeeping packet was sent are now discarded rather than overwriting the last one.

COS DCE Boot FSW changes from v01.00 to v01.02

1. Added 20 msec timer byte to augment the 1-second timer. One-second timer still displayed in housekeeping.

2. Added check for command words with a leading '1' and some non-zero bits elsewhere

3. Removed masking of the LS-bit of the address so that odd-boundary words may be sent to upload area and command packet.

4. Added counter for "command words received but not stored" as well as a 32-bit location to store the last "non-stored" word

5. Changed the means of determining whether a command opcode had been received FROM looking for address 0440 TO looking for a non-zero value at location 0440h (actually 2440h, but only the boot code 8051 knows that I translated the address).

6. Only reinitialize external RAM (i.e., copy patchable constants from CODE to XDATA) on power-on reset (it used to be for either reset).

7. Diagnostic 07 has been changed to 17 -- bringing an unused diagnostic out of retirement. It means "boot code has experienced unexpected stack growth".

8. After building the housekeeping packet, I now clear the 14 command words (the 99.99% solution).

9. Housekeeping packets are sent upon receipt of any opcode (valid or not). Formerly, they were only sent upon receipt of a valid command packet (all 14 words).

10. I no longer zero out the previous CRC value of the three background regions (ROM, LCA, UCA) while computing a new value. The LFDCRC command still does this so that operators will see that it is still in progress.

11. I now treat commands with opcode less than 80h as an ill-formed command packet (i.e., I don't increment command received counter). Formerly, opcodes less than 80h were treated as illegal commands, but still as a command received.

12. Rather than ending housekeeping building ONLY upon receipt of a housekeeping script opcode of 00h, I now stop building housekeeping if ANY invalid opcode is encountered. This allows us to completely trash external RAM and not get into an endless loop of doing nothing.

13. HST error parameters are now displayed little-endian in order to be consistent with all other multi-byte quantities in housekeeping.

14. Moved COS_BOOT_TBL -- the look-up table for the 13 boot command functions -- back into CODE space (it was copied to XDATA as a patchable constant). This was the only patchable constant which, if trashed, would hang the system. By leaving it in CODE space (PROM), it cannot be trashed. So, no destruction of external RAM will hang the boot code.

15. Version number changed from 01.00 to 01.02 and put in proper little-endian form.

16. HST error parameter LFMCRC wrongly included where I should have had LFMROM. It is now fixed.

17. Removed the $NOLIST assembler directive from those macros which created code -- thereby making the listing files show all bytes of code.